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Table 7-15 · Interrupt Control Register 48 Hex (MASTER = 0)
Bit(s)
15
31:16
Type
RW
RO
Description
External Interrupt Enable
Writing a '1' to this bit enables support for the external interrupt signal. Writing a '0' to this bit disables external
interrupt support.
Reserved. Set to 0.
Table 7-16 · FIFO Status Register
Bit(s)
2:0
3
6:4
7
10:8
11
14:12
15
18:16
19
22:20
23
31:24
Bit(s)
Type
Type
RO
RO
RO
RO
RO
RO
RO
RO
RO
RO
RO
RO
RO
Description
Number of words queued inside the core for BAR 0
External FIFO status for BAR 0; 0 = empty, 1 = non-empty
Number of words queued inside the core for BAR 1
External FIFO status for BAR 1; 0 = empty, 1 = non-empty
Number of words queued inside the core for BAR 2
External FIFO status for BAR 2; 0 = empty, 1 = non-empty
Number of words queued inside the core for BAR 3
External FIFO status for BAR 3; 0 = empty, 1 = non-empty
Number of words queued inside the core for BAR 4
External FIFO status for BAR 4; 0 = empty, 1 = non-empty
Number of words queued inside the core for BAR 5
External FIFO status for BAR 5; 0 = empty, 1 = non-empty
Reserved. Set to 0.
Table 7-17 · PCI Address Register 50 Hex
Description
These two bits set the lowest two bits of the PCI address. For normal DWORD-aligned transfers, these two bits
1:0
31:2
112
RW
RW
should be '00'. They may be set to non-zero values to alter the requested burst order for memory accesses or to specify
a byte address for I/O accesses.
This location contains the PCI start address and will increment during the DMA transfer.
If using 64-bit transfers, bit 2 should also be set to 0.
v4.0
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